vlsi front-end design engineer

From: suman boppana and having desired in design field for working with a reputed company where my skills may add a brick to increase the company growth
Date: Tuesday, March 14, 2006
Time: 01:13 AM

Resume

CURRICULUM VITAE B. SUMAN Email: suman0316@yahoo.com Mobile. No: 91- 9885950862 OBJECTIVE To attain a position of excellence and to seek a creative and challenging career that utilizes my skills with cooperative work culture that leads to the steady growth of the company. TRAINING EXPERIENCE PG Diploma in Sandeepani School of VLSI Design. (A Training Division of CG CoreEL Programmable Solutions Ltd., Bangalore). (Authorized Training Center of Xilinx and Mentor Graphics Ltd). TECHNICAL SKILLS: > Fundamentals of FPGA design > Design for performance > Familiar with Incremental design concepts > RTL, Test bench coding using HDL. HARDWARE DISCROPTION LANGUAGE : EDA TOOLS >> Verilog HDL >> ModelSim >> VHDL >> Leonardo Spectrum XILINX TOOL > ISE (Project Navigator 7.1i) Worked on Spartan III OPERATING SYSTEMS : Linux (red hat), Windows NT/98/00/XP. OTHERS : C, C++, MS Office, MatLab (basics). EDUCATIONAL QUALIFICATIONS > Completed Bachelor of Technology in Electronics and communication engineering from JNTU University, India - June 2005 with 65% > Completed Inter (10+2) from Board Of A.P, in June 2001 with 82% > Completed S.S.C (10th) from Board Of A.P, in June 1999 with 69% PROJECTS: >> Industrial Security Using Embedded System DESCRIPTION:The main idea behind this project is to detect fire accidents, the intruder and scanning for metal or weapon and alert corporate, for which an embedded system is developed so that the security is maintained all the time Tools : LAB VIEW (software), 8051 hardware kit, Kiel (soft). Language : Embedded ‘c’ language. >> Design Of Digital Alarm Clock DESCRIPTION:Designed a Digital Alarm Clock using Verilog HDL, which can display Current time, load new time, set alarm time, sound alarm. Test benches were written for all the modules and the top-level module and functionally it was verified. The design was synthesized, placed & routed and the bit file was generated, which is downloaded on to the XILINX target device Spartan3. HDL :Verilog. Tools :Xilinx ise(7.1i),Leonardo Spectrum,ModelSim. >> Design Of Petrol Bunk Meter Using Seven Segment Display DESCRIPTION:This is a prototype of real time petrol bunk meters, which are used now a day. The design has been develop using VHDL, which can display Market Price, Customer’s request in Money or in Liters; it can count the amount of liters and the respective money in parallel. Functional block of counting logic is developed on FPGA and the design has been passed. The design is so sophisticated that all the four displays are displayed using only four seven segments display of one row. In advance the counting is stopped when the target is reached either in liters or in money. The bit file was generated and downloaded into XILINX device Spartan3. HDL :VHDL. Tools :Xillinx ise(7.1i),Leonardo Spectrum,ModelSim. >> Designing Flexible, Fast CAMs with Spartan Family FPGAs Content Addressable Memory (CAM) allow a fast search for specific data in a memory. Each application has different CAM requirements .A CAM depth and width based upon LUTs configured as Shift Registers. This application describes a fast CAM design finding a match in a single clock cycle. The CAM depth is also expandable (depending upon number of slices per column in FPGA family) providing a real flexibility. HDL :Verilog. Tools :Xilinx ise(8.1i),Leonardo Spectrum,ModelSim. PERSONAL DETAILS Contact Address : s/o B.Nagamalleswera Rao , T-1/3 Hostel Lines, Mud fort, Secunderabad-500003. Date of Birth : 16/03/1983 Languages Known : English, Hindi and Telugu I hereby declare that all the above statements made are correct to my knowledge Suman B

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